Data can be communicated between computers and within computers using various protocols for communicating the data. Data can be synchronously communicated using a global clock that is provided to both the sources and the destinations of the data. Each destination can sample the current value from a bus connecting the sources and the destinations at transitions of the global clock and each source can transmit the next value to the bus at these transitions of the global clock. Because the next value driven to the bus takes some time to propagate from the sources to the destination, the period of the global clock can be limited by the propagation times between the sources and the destinations. This limitation on the clock period can limit the bandwidth of data transfer by the bus.
Data may also be synchronously communicated using a source-synchronous clock. A source of data may transmit the next value of the data to a bus connecting the source to one or more destinations. The next value of the data to be communicated may be transmitted by the source to the bus at transitions of a clock, and a version of the clock may also be transmitted to the bus along with the data. Each destination may sample the current value from the bus at transitions of the version of the clock received from the bus. Because the data and the clock propagate together from the source to each destination, the length of the propagation time between the source and the destinations can be eliminated as a limiter of the bandwidth of data transfer by the bus. However, the differences in propagation times, or skew, between the source-synchronous clock and each data bit of the bus can limit the bandwidth of data transfer by the bus. The skew can be reduced by transmitting multiple copies of the source-synchronous clock for various subsets of the data bits of the bus; however, each source-synchronous clock adds overhead that reduces the effective bandwidth per signal of the bus.
Higher bandwidth data communication than provided by global clocking and source-synchronous clocking can be achieved by transferring the clock encoded in the data transferred. Typically, encoded clock communication uses a point-to-point communication channel, with one source and one destination. The clock and data can be encoded using an 8b/10b encoding. The 8b/10b encoding encodes each 8 bits of data in a 10 bit symbol and the bits of the symbols can be serially communicated through the channel using differential signaling. The destination may use a phase-locked loop to recover the transmit clock from the frequent transitions of the encoded symbols. Because the clock is encoded in the data, skew between the clock and the data can be eliminated as a limiter of the bandwidth of data transfer by the channel. However, the jitter of the transmit clock and the recovered clock may misalign the sampling of the data at the destination and thereby limit the bandwidth of data transfer by the channel. In addition, the effective bandwidth is reduced by the twenty percent overhead of the 8b/10b encoding.
Specialized analog circuits are required to encode, transmit, receive, and decode encoded clock data communications. For example, phase-locked loops are specialized analog circuits that are expensive and time-consuming to design, occupy a significant amount of area on an integrated circuit, and dissipate a significant amount of power during operation. The scaling of generations of integrated circuit fabrication processes is making the design of these specialized analog circuits more expensive and more time-consuming. For example, the scaling of fabrication processes is reducing the power supply voltage, and current fabrication processes already implement special transistors supporting a higher power supply voltage for analog circuits. Even with these special transistors supporting a higher power supply voltage, the design of analog circuits is becoming more difficult and time-consuming with each process generation.
The present invention may address one or more of the above issues.